The integration of MOSFET structures and bipolar transistors on a single substrate has become very desirable. In addition, silicon on insulator (SOI) technology offers the highest performance for a given feature size due to the minimization of parasitic capacitance.
As is well known in the art, digital and linear functions are often performed by integrated circuits using either bipolar or metal-oxide-semiconductor (MOS) technology. Bipolar integrated circuits, of course, provide higher speed operation and greater drive currents than the MOS circuits, at the cost of higher power dissipation, especially when compared against complementary MOS (CMOS) circuits. Recent advances in manufacturing technology have allowed the use of both bipolar and CMOS transistors in the same integrated circuit (commonly referred to as BiCMOS devices). Further exploitation of the high current driving capabilities of the bipolar transistor is important to obtaining even higher levels of bipolar or merged bipolar CMOS integration.
Resistors for BiCMOS integrated circuits have typically been diffused resistors. One process for forming a diffused resistor in a semiconductor device uses a 0.8 micron BiCMOS process. In that process, a 600 .OMEGA./.quadrature. diffused resistor results. The length of the resistor is defined by a polysilicon layer which blocks silicidation of the resistor body. One of the downfalls of this resistor is its large parasitic capacitance. This parasitic capacitance slows signal flows through the circuit. Parasitic capacitance exists between the resistor and the polysilicon layer above it as well as between the resistor and the adjacent N-well.
For more BiCMOS integrated circuits that have use in advanced technologies such as asynchronous transfer mode (ATM) telephone switching technology as well as generic application specific integrated circuit (ASIC) technologies, parasitic capacitance problems degrade circuit performance to less than acceptable levels.